1. Field of the Invention
This invention relates generally to semiconductor integrated circuit memory devices such as flash electrically erasable programmable read-only-memory (EEPROM) devices and more particularly, it relates to an improved low supply voltage negative charge pump for generating a relatively high negative voltage to control gates of selected memory cells via wordlines in an array of flash EEPROM memory cells during flash erasure.
2. Description of the Prior Art
In U.S. Pat. No. 5,406,517 to Chung K. Chang et al. issued on Apr. 11, 1995, there is described and illustrated a distributed negative gate power supply for generating and selectively supplying a relatively high primary negative voltage to control gates of memory cells in selected half-sectors via wordlines in an array of flash EEPROM memory cells during flash erasure. The '517 patent is assigned to the same assignee as in the present invention and is hereby incorporated by reference in its entirety. In FIG. 1 of the '517 patent, there is shown a block diagram of the distributed negative gate power supply 10 which includes a separate large main pump circuit 16 and a plurality of relatively small-size, single-stage distribution sector pump circuits 18a-18p for selectively distributing the primary negative voltage NEGP.
In FIG. 2 of the '517 patent, there is shown a block diagram of the main pump circuit 16 of FIG. 1. The main pump circuit 16 includes two identical negative pumping circuits 20a and 20b which are driven by a respective clock circuit 22a and 22b for generating the relatively high primary negative voltage NEGP. The negative pumping circuit 20a is associated with the left side of the array, and the negative pumping circuit 20b is associated with the right side thereof. In FIG. 1 of the present invention, there is depicted a schematic circuit diagram of the negative pumping circuit 10, which is similar to the one in FIGS. 3(a) and 3(b) of the '517 patent.
The negative pumping circuit 10 includes four stages 12, 14, 16 and 18. An output transistor 20 is coupled to the output of the fourth stage 18 for generating the relatively high primary negative voltage NEGP on line 22, which is approximately -10.5 volts. An output buffer stage 24 is also coupled to the output of the fourth stage 18 for generating the secondary negative voltage NEGSm, which is approximately -14 volts. The input of the pumping circuit 10 is at input node "pmps." An N-channel pump-select transistor 26 has its drain connected to the input node "pmps," its gate connected to receive the erase signal ER and its source connected to the lower power supply potential VSS (ground).
The first stage 12 is formed of a P-channel pass transistor P11, a P-channel initialization transistor P12, a P-channel pre-charge transistor P13, and a pair of coupling capacitors C1, C7. The N-well of the P-channel transistors P11-P13 are connected to the upper power supply potential VPP. The coupling capacitor C1 is coupled between the node BB and an input node 28 for receiving the clock signal PHI1. The coupling capacitor C7 is coupled between the node AA and an input node 30 for receiving the clock signal PHI2A. Each of the coupling capacitors C1 and C7 is formed of a capacitor-connected P-channel MOS transistor which is operated in the inversion region.
The second stage 14 is identical in its construction to the first stage 12 and includes P-channel transistors P21, P22 and P23 and coupling capacitors C2 and C8. The N-well of the P-channel transistors P21-P23 are connected to the upper power supply potential VPP. The coupling capacitor C2 is coupled between the node D and an input node 32 for receiving the clock signal PHI2. The coupling capacitor C8 is coupled between the node B and an input node 34 for receiving the clock signal PHI1A.
The third stage 16 is likewise identical in its construction to the first stage 12 and includes P-channel transistors P31, P32 and P33 and coupling capacitors C3 and C9. The coupling capacitor C3 is connected between the node G and the input node 28 for receiving the clock signal PHI1. The coupling capacitor C9 is connected between the node E and the input node 30 for receiving the clock signal PHI2A. It will be noted that the N-well of the P-channel transistors P31, P32 and P33 are tied to the negative well voltage VNWn (approximately 0 volts during erase) rather than the supply potential VPP so as to prevent junction breakdown.
The fourth stage 18 is quite similar in its construction to the first stage 12 and includes P-channel transistors P41, P42 and P43 and coupling capacitors C4 and C10. The coupling capacitor C4 is coupled between the node J and the input node 32 for receiving the clock signal PHI2. The coupling capacitor C10 is connected between the node H and the input node 34 for receiving the clock signal PHI1A. Each of the coupling capacitors C2-C4 and C8-C10 is likewise formed of a capacitor-connected P-channel MOS transistor which is operated in the inversion region. The output transistor 20 has its source connected to the node J and its drain connected to the output line 22 for generating the negative voltage NEGP. The gate of the transistor 20 is connected to an internal node K. The N-well of the transistor 20 is also connected to the N-well voltage VNWn.
One of the disadvantages in this prior art negative pumping circuit 10 is that each of the charge pumping stages is formed of a pair of capacitor-connected P-channel MOS transistors and a P-channel pass transistor. Since the P-channel transistor devices have such a large body-effect coefficient and the back-bias (sometimes referred to as "source bias"--V.sub.sb) is so high, the threshold voltage V.sub.tp can be as high as -3.0 volts when used as charge passing devices in a negative charge pump. As a result, the four-stage charge pumping circuit 10 of FIG. 1, even with the voltage threshold cancellation circuit (i.e., P12, P13 and C7 for the first stage), is thus made impractical when the power supply voltage VCC is reduced to +3.0 volts or lower, unless the clock signals themselves are pumped to a higher voltage than the power supply voltage VCC. In addition, the prior art negative pumping circuit suffers from another disadvantage due to the fact that the capacitor-connected P-channel MOS transistors are functioning as an inversion capacitor which has a higher initialization voltage.
The present invention represents a significant improvement over the prior art negative pumping circuit in the main negative pump circuit of the distributed negative gate power supply as discussed above in the '517 patent. The low supply voltage negative charge pump of the present invention is used for generating a relatively high negative voltage during flash erasure in which a supply voltage of +3.0 volts or lower is being used. The low supply voltage negative charge pump includes a plurality of charge pump stages each having an intrinsic N-channel transistor formed in separate p-wells in order to minimize the body-effect coefficient. As a result, the negative charge pump is capable of operating at lower supply voltages.